In the integrated circuit field, it is of course beneficial to fabricate as many active devices a given area of semiconductor material as possible, increasing the complexity of the functions capable by individual circuits, as well as increasing the performance of the circuits. This density is not only dependent upon the the size of the active regions (e.g, transistor sizes), but also on the area required to isolate transistors from one another. Prior techniques for the formation of isolation regions between active areas on a semiconductor chip include the well known LOCOS technique, and improvements thereto such as that described in U.S. Pat. No. 4,541,167 assigned to Texas Instrument Incorporated. Such techniques provide isolation by way of providing a transistor which is held in the "off" state, and which has a very high threshold voltage due to the dielectric thickness (field oxide thickness) underlying the gate, and due to channel-stop implants under the field oxide.
In addition, complementary-metal-oxide-semiconductor (CMOS) technology has gained popularity in the fabrication of integrated circuits due to the reduced power consumption and competitive performance of such circuits. CMOS circuits are often formed by p-channel transistors formed in n-type wells or tanks, and n-channel transistors formed in p-type wells or tanks. The wells of opposite conductivity type are often adjacent, requiring isolation therebetween. Junction isolation may be provided by biasing the n-well positive relative to the p-well, reverse-biasing the junction therebetween. Such junction isolation presents parasitic capacitance to the circuit, however, as well as requiring a certain amount of otherwise unusable surface area.
Modern isolation techniques have used trenches etched into the semiconductor substrate. A first example of such trench isolation, incorporated into a bipolar integrated circuit, is described in copending application Ser No. 932,752, filed Nov. 19, 1986 and assigned to Texas Instruments Incorporated. The trench isolation provided in this example uses a polysilicon plug within the trench, to overcome the problems of localized stress from the trench arising due to the dissimilarity of the coefficients of thermal expansion of the substrate (e.g., silicon) to the insulator (e.g., silicon dioxide), as well as the stresses from the formation of a filling oxide. The polysilicon plug filling the trench after formation of the sidewall dielectric serves to minimize the stress, as it minimizes the formation and volume of the oxide within the trench. In this example, however, the layout of the circuit must take into account the possiblity of leakage from an overlying conductive layer into the plug. Since only a relatively thin dielectric is provided over the trench plug, stresses from subsequent process steps such as contact etch, silicidation, and metal deposition and sinter can damage the thin dielectric, especially where a contact via is formed over the trench. An extreme overetch of such a contact via overlying the can thin the dielectric layer to the extent that leakage to the plug can result. For circuits using such trench construction, therefore, overlying contacts are generally prohibited, requiring less efficient circuit layouts.
From a leakage standpoint, it is beneficial therefore to provide a thick dielectric over the top of the polysilicon plug in the trench. An example of such a thicker dielectric over a filled trench is described in copending application Ser. No. 923,454, filed Oct. 27, 1986 and assigned to Texas Instruments Incorporated. In this example, an oxide layer is grown over the trench after it has been filled with a polysilicon plug. While resulting in a thicker oxide over the filled trench, such oxide growth creates significant stress on the trench structure during its growth. This stress results from the growth of oxide at the sidewalls of the trench and at the plug, near the top of the trench. In effect, a wedge of oxide is attempting to grow in the space between the plug and the substrate, such space already containing a sidewall oxide, resulting in similar stress problems as that encountered at the bird's beak of LOCOS isolation.
It is therefore an object of this invention to provide a method for fabricating an integrated circuit using trench isolation which overcomes the above problems.
It is another object of this invention to provide such a method which may be utilized in bipolar, MOS and BiCMOS structures.
It is yet another object of this invention to provide such a method in such a manner that an additional photolithography operation is not required for the additional insulating layer.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.